Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Heretofore, programmable logic of an FPGA (“FPGA fabric”) was on a same die as all other circuitry of the FPGA. However, while the FPGA fabric for example tended to push the state of the art of lithography for manufacturing integrated circuits, many other components of the FPGA did not. Thus, while some components of an FPGA may shrink with each new available lithographic process technology, other components do not likewise shrink with such newly available lithographic process technology.
This incongruity had significant cost implications. For example, lithography pushing the state of the art of manufacturing tends to involve transistors which are more sensitive to variations in semiconductor processing. Thus, even though base components manufactured with a less aggressive lithography would yield at a substantially higher rate, semiconductor dies were subject to the lower yield rate of the more aggressive, and thus more sensitive, semiconductor processing. Furthermore, complications associated with the manufacture of substantially disparately sized components may involve complications with respect to etch depths, number of metal layers, and other known process integration issues. Lastly, semiconductor process technology that pushes the lithographic state of the art for manufacturing tends to be more expensive per unit area of semiconductor die.
Accordingly, it would be desirable and useful to provide an integrated circuit device that avoids one or more of the above-mentioned problems.